To inspect for reticle defects, in the production of large scale semiconductor devices, a reticle die pattern is usually imaged on a bare substrate such as a silicon wafer using a photoresist process. The resist image is then magnified by a high resolution camera for pattern inspection. The entire image is divided into fields which in turn are digitized into a pixel matrix. Depending upon the image intensity, each pixel can be assigned a grey level in a manner similar to the picture elements of a black and white television image. The number of grey levels and the number of pixels will be dependent on the resolution required. Typically, there are more than 10 grey levels and the pixels are micron or sub-micron in size. If the digitized images of two different dice on the wafer are compared, random defects generated by the lithographic process will be highlighted. However, to detect repeating defects, the image must be compared with the design tape data which is used to define the reticle.
During inspection, the design tape data is divided into exactly the same number of fields as the real resist image. The inspection sequence starts with the first frame where, by using computer simulation, process specific parameters such as background grey level, pattern grey level, design dimension bias and corner rounding can be accounted for and the synthetic image can be made to match the real resist image. These two images are compared pixel by pixel element within each corresponding field and the defects, both random and repeating, are detected. Repeating defects are the defects common to each identical die on the wafer.
As the wafer processing progresses, the composite pattern of all previous levels on the die becomes very complex. The resist pattern of the current layer is no longer on a uniform background. Both the resist image and the background layers reflect varying degrees of grey. Though it is possible to overlay, in the computer memory, the design tape data of the current layer and the computer simulated images of all previously formed layers, the grey levels of the pixel elements cannot be simulated and the synthetic image cannot be accurately constructed. Therefore, the current method is restricted to a comparison of design data with a single level resist image of the current layer on a bare substrate.
Microscopically, the surface of the device under inspection is not smooth. In comparison to the device features being imaged, severe topographies exist. Also, the reflectivity of the surface changes from location to location due to changes in the underlying structures. As a result, it is common knowledge that resist imaging on a substrate of this nature will be significantly different from the idealized environment of a flat bare substrate. Consequently, defects on the wafer created by imperfections on the reticle may not show up on the bare substrate employed by the current inspection method. It is therefore desirable to compare the design tape data with the resist pattern on a real device wafer so that automatic in-line wafer inspection may be realized.